The present invention relates to motion detection technology for processing a video signal. More particularly the present invention relates to a motion detection circuit and a method in which the spatial information of a video signal is represented by more than one bit. Furthermore, the present invention calculates spatial information in a plurality of directions to accurately detect motion and efficiently uses a frame memory.
Generally, in video signal processing equipment (such as a high definition television, a video tape recorder, and a camera) motion detection is used for encoding a video signal. To encode the signal, an adjacent interframe difference signal is encoded to compress motion image data. Also, in order to improve picture quality, the picture is divided into frame blocks of a predetermined size, an adjacent interframe motion is found, the picture is shifted by the moved distance, and an interframe motion is reduced. In the above steps, finding the interframe motion per frame block is called "motion estimation," and the distance moved is called a "motion vector." Also, using the frame block of a previous frame to compensate for the movement of the currently processed frame block is called "motion compensation." The previous frame corresponds to the frame which is adjacent to the current frame block and was processed immediately before the current frame block is processed.
A conventional and basic motion detection circuit uses a frame memory to obtain interframe difference signals between frames. In addition, the motion detection circuit determines whether the video signal is in a motion area or a stationary area by comparing the interframe difference signal with a predetermined reference value.
However, since such a conventional motion detection circuit requires a frame memory, the cost of a conventional motion detection circuit is relatively high. Thus, a conventional motion detection circuit has not been used in typical video equipment except for an improved definition TV or an enhanced definition TV.
Also, most video equipment process a video signal in a spatial domain (i.e a horizontal-vertical two-dimensional domain). However, still area processing is advantageous for processing a signal using a frame memory, while motion area processing is advantageous for processing a signal in time domain. Thus, it is not efficient to process a signal in only a spatial domain. In order to effectively solve such a problem, it is necessary to simplify the hardware and lower the costs of the motion detection circuit.
FIG. 1 is a circuit diagram of a conventional one-bit motion detection circuit which attempts to solve some of the above-described problems. As shown in FIG. 1, the conventional motion detection circuit includes a bit limiter 1 which compares an 8-bit input video signal Y.sub.in with a predetermined reference value and converts the input video signal Y.sub.in into a 1-bit signal according to the result of the comparison. A memory portion 2 is connected to the bit limiter 1 and includes a line memory 2A for storing the multiple outputs of the bit limiter 1 which form an entire row of pixels. The memory portion also includes a delay 2B for delaying the output of the line memory 2A for one sampling period, and a delay 2C for delaying the output of the bit limiter 1 for one sampling period. A shift register 3A is connected to the output of the line memory 2A to shift the output of the line memory 2A by one bit. Also, two shift registers 3B and 3C are connected in series to the output of the delay 2C to shift the output of delay 2C by two bits. In addition, three shift registers 3D through 3F are connected in series to the output of the bit limiter 1 to shift the output of bit limiter 1 by three bits.
The outputs of delay 2B and shift registers 3A, 3C and 3F are applied to an adder 4. The adder 4 adds the input signals and outputs a 4-bit signal to a frame memory 5 and a comparator 6. The frame memory 5 stores the 4-bit signal output from adder 4 according to an input pixel clock and a frame clock. The frame memory 5 outputs the 4-bit signal which was previously generated for the adjacent frame block to the comparator 6. The comparator 6 compares the output of the adder 4 with the previously stored signal output from the frame memory 5 and outputs a motion signal which represents whether the input video signals are in a moving area or a stationary area.
If an 8-bit input video signal Y.sub.in is input to the conventional circuit constructed above, the bit limiter 1 compares whether the input video signal Y.sub.in is larger or smaller than the decimal number 127. If the input video signal Y.sub.in is smaller than 127, the bit limiter 1 outputs a zero. If the input video signal Y.sub.in is larger than 127, the bit limiter 1 outputs a one. Thus, the 8-bit video signal is transformed into a one-bit signal that is applied to the line memory 2A, the delay 2C, and the shift register 3D.
FIG. 2 shows a sample constitution diagram which represents a conventional encoding technique. The sample composition diagram comprises a plurality of frame blocks. Each frame block is divided into a 2.times.2 block unit constituted by two horizontal pixels and two vertical pixels. The two upper horizontal pixels of each frame contain the samples a and b, and the two lower horizontal pixels of each frame contain the samples c and d.
Each 4-bit signal output by the adder 4 represents a 2.times.2 frame block as follows. First, the motion detecting circuit inputs an input video signal Y.sub.in representing a pixel in row x, column y (i.e. input video signal (x,y)). The bit limiter 1 then converts this input video signal (x,y) into a resultant one bit signal (i.e. one bit signal (x,y)), and the one bit signal (x,y) is stored in the line memory 2A. Second, the input video signal (x,y+1) is input, and the resultant one bit signal (x,y+1) is stored in the line memory 2A.
After the all of the input video signals Y.sub.in have been input for row x, the input video signals Y.sub.in for row x+1 are input. Eventually, the input video signal (x+1,y) is input, and the bit limiter 1 outputs the resultant one bit signal (x+1,y) to the delay 2C. At this time, the line memory 2A also outputs the one bit signal (x,y) to the delay 2B.
Subsequently, the input video signal (x+1,y+1) is converted into the one bit signal (x+1,y+1). This one bit signal (x+1,y+1) is output from the bit limiter 1 as sample d. At the same time the one bit signal (x+1,y+1) is output from the bit limiter 1, the delay 2C outputs the one bit signal (x+1,y) as sample c, the line memory 2A outputs the one bit signal (x,y+1) as sample b, and the delay 2B outputs the one bit signal (x,y) as sample a.
Then, sample d is shifted three times by shift registers 3D to 3F to form the four bit word d000. Sample c is shifted two times by shift registers 3B and 3C to form the four bit word 0c00. Sample b is shifted once by shift register 3A to form the four bit word 00b0. Finally, sample a is not shifted at all to form the word 000a. Subsequently, the these signals are input to the adder 4, and the adder 4 adds the signals to form the 4-bit codeword dcba. This 4-bit codeword can be expressed as 2.sup.0 a+2.sup.1 b+2.sup.2 c+2.sup.3 d.
After the 4-bit codeword is formed, the 4-bit codeword is simultaneously stored in the frame memory 5 and output to the comparator 6. The comparator 6 compares the output current codeword output by the adder 4 with the previous code word output by the frame memory 5. The previous codeword refers to the last codeword that was generated during the sampling of the input video signals (x-2,y), (x-2,y+1), (x-1,y), (x-1,y+1). Depending on the relationship between the previous codeword and the current codeword, the comparator is able to determine if motion is detected. If motion is detected, the comparator 6 outputs a zero. If no motion is detected, the comparator 6 outputs a one.
As described above, the conventional circuit uses a signal which is converted into a one-bit signal to obtain a one-bit motion signal based on the frame difference. However, since the input video signal Y.sub.in is already converted into the one-bit signal before it is processed, accurately detecting motion is not possible even though four pixels on the field are used. In other words, since the 8-bit input video signal Y.sub.in is reduced to a one-bit signal or a signal with less than 8-bits, the chance of an error due to noise can be reduced. However, in such a conventional circuit, moving area processing is extremely limited as compared to a similar level of stationary area processing. Thus, the overall picture quality is degraded. As such, erroneously interpreting the moving area as the stationary area more severely degrades the picture quality than if the stationary area is erroneously interpreted as a motion picture domain.
For example, if the moving area is misinterpreted as the stationary area and the previous frame signal is used as an interpolation signal in case of being interlaced to progressive scan conversion, the interlined distance becomes irregular and degrades the picture quality. Furthermore, the more severe the motion, the more the picture is degraded. However, when the stationary area is interpreted as the moving area, intra-field processing is performed. Therefore, the vertical resolution of a picture is reduced but the misinterpretation does not severely degrade the picture quality.
In FIG. 1, although the motion detection is performed according to four horizontal-vertical samples and an output signal is processed using a 5-point median filter at the next stage (not shown), the above problem persists until the length of the bits is increased since the above problem is due to the small length of bits representing the interframe difference. However, when the length of the bits is increased, the hardware cannot be simplified because the capacity of the frame memory must be increased.